The present invention relates to CMOS imagers and, more particularly, to correlated double sampling circuits employed by CMOS imagers.
Present solid-state image sensors are created from essentially three different technologies. Self-scanned diode array; charge injection device (CID) arrays; and charge-coupled device (CCD) arrays. Each of these three technologies will be produced by a semiconductor process that has inherent limitations which limit the achievement of higher integration. The art of solid state image sensors has evolved to the point where a CMOS process can be employed in the production of solid state image sensors. The use of CMOS technology allows higher integration resulting in both analog and digital circuits being integrated within the same silicon chip as the sensor array. Higher integration, additionally, allows for the achievement of higher resolution and higher speed. During normal use, hundreds of different signals, representing individual channels are simultaneously present at the output of the sensor array. These signals need to be processed and then converted into a digital signal. However, process variations (which exist in any of the processes used to manufacture these devices and cannot be eliminated) create offsets between the various circuits that are dedicated to the individual columns generating what is referred to as xe2x80x9ccolumn pattern noisexe2x80x9d or xe2x80x9cfixed pattern noisexe2x80x9d.
Imaging systems desiring high resolution and high speed, such as 10-bit resolution, 24 frame per second, need to have xe2x80x9cfixed pattern noisexe2x80x9d removed before analog to digital conversion can be performed for any large size image array. Prior art devices typically employ a double sampling circuit for each column within a sensor to remove fixed pattern noise. These prior art correlated double sampling circuits allocate a double sampling circuit for every column and as a result have disadvantages in terms of: higher power dissipation; slower speed; only a partial removal of fixed pattern noise; more silicon area needed to provide a double sampling for each column; a more complicated process involved to create the additional circuitry; and higher cost.
From the foregoing discussion, it should be apparent that there remains a need within the art for a method and apparatus that can be employed within a CMOS environment to perform CDS without requiring large amounts of silicon area and power. These and other problems are addressed by the present invention as discussed below.
The present invention pertains to a new Column Correlated Double Sampling (CDS) circuit that provides double sampling for each column by placing the first sampling circuit in the column itself and the second sampling circuit is shared between the various columns resulting in doubling sampling circuit that requires much less silicon space, is more economical to produce, requires less power dissipation, operates at higher speeds, improves the removal of fixed pattern noise, and requires less process steps to create than prior art devices.
The CDS circuit of the present invention is intended to satisfy various design parameters, including: very small size; a 70% increase in speed; lower power dissipation; and more importantly, a substantial reduction in fixed pattern noise compared to prior art devices. Except for the standard control clocks, including a reset clock, a signal clock and a column select clock, no other control clocks are required. These standard clocks are those typically required for any imager array application employing a semiconductor based imager and can be provided by a relatively simple digital control circuit. The CDS circuit as envisioned by the present invention can run at speeds as high as 30 million samples/second with power dissipation less than 13 mW (for 1200 column array). The present invention, potentially, removes up to 100% of the fixed pattern noise.
These and other features and advantages of the present invention are provided by a correlated double sampling unit comprising: an image sensor having a plurality of photodetectors arranged in a series of rows and columns; a row addressing circuit; a column addressing circuit; a first sample and hold circuit allocated for each of the columns; a transfer circuit operatively connecting each of the columns to the sample and hold circuit that is allocated to that column; and a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits.